Such a semiconductor product may be, for instance, a flash memory product comprising a plurality of memory cells like NROM (nitride read only memory) or alternative kinds of non-volatile memory cells (like floating gate cells). In a flash memory product, the memory cells are programmable individually selectively to the respective other memory cells. When information is deleted, all memory cells of the same particular sector are commonly deleted at the same time. The memory cells of the respective sector may be later reprogrammed individually.
The memory cells of a flash memory are arranged in a virtual ground array or in other array architectures. Each memory cell is connected to two respective bitlines running parallel to one another. In a virtual ground array each bitline is connected to memory cells arranged on opposed sides of the bitline. Connection between the bitlines and the memory cells is provided by contact structures that comprise first contacts called “local interconnect”. The local interconnects are arranged in rows extending perpendicular to the direction of the bitlines. In a direction parallel to the bitlines, a bitline is connected to one respective local interconnect of every other row of local interconnects. Furthermore, in every other row, the local interconnects have a lateral offset relative to the lateral positions of the local interconnects of the other rows of local interconnects. Each bitline is connected to local interconnects of every other row (for instance of a first, third, fifth, etc., row) whereas the bitline is passing over memory cells of a second, fourth, sixth, etc., row of local interconnects without being connected to the local interconnects of the second, fourth and sixth rows.
In a virtual ground array, the bitlines are connected to the memory cells via contact structures that, according to prior art, comprise a first contact called “local interconnect”. The local interconnects are contact hole fillings provided in a dielectric layer above a substrate. The local interconnects are wide via contacts having a main extension in a first lateral direction perpendicular to the direction of the bitlines. They serve to connect two line-shaped active areas to a bitline. The active areas are doped regions providing the source/drain regions and the channel regions and, in a virtual ground array, are formed in lines or stripes separated from one another by trench isolation fillings like shallow trench isolations (STI). The trench isolation fillings as well as the active areas are formed line-shaped seen from top view on the semiconductor substrate. When the bitlines are formed, they are positioned such that they are running parallel to the active areas but are, for instance, located at same lateral positions as the shallow trench isolation fillings, that is at centered lateral positions between two respective adjacent line-shaped active areas.
The local interconnects contacts, in direction perpendicular to the active areas, extend beyond the bitlines on opposed sides of the respective bitline. In particular, the local interconnects extend to the active areas next to the bitline positioned on opposed sides of the bitline. Typically, a local interconnect has a width being approximately three times the width of the bitline since the width of the active areas and the width of the trench isolation fillings between the active areas correspond to one another.
In order to connect the bitline to the local interconnects, which are much wider than the bitlines, bitline contacts (the “contacts to interconnect”) are formed according to prior art. To this end, a dielectric layer is deposited and via contact holes are etched in the dielectric layer so as to expose a portion of an upper surface of the local interconnects. The contact holes in the second dielectric layer are then filled with conductive material. By planarizing the conductive material, the contacts to interconnect are formed. Subsequently, the bitlines are formed.
In the process of manufacturing the semiconductor product, a substrate is provided and a plurality of line-shaped active areas as well as a plurality of line-shaped trench isolation fillings disposed between respective two active areas are formed in the substrate. Subsequently, a layer stack comprising a bottom oxide layer, a charge-trapping layer like a silicon nitride layer, and a top oxide layer are deposited. Wordlines are then formed by depositing one or more conductive layers and a cap nitride layer for forming gate stacks. These layers are then pattered thereby forming a plurality of wordlines. Sidewall spacers are then formed on sidewalls of the wordlines in a conventional manner.
Thereby a plurality of wordlines arranged at a distance from one another and running, at least in a region of the substrate surface, along a first direction, are provided. In spaces left between respective two wordlines the contact structures (the local interconnects) are to be formed thereafter. Conventionally, a dielectric layer is deposited and etched so as to form a plurality of filling structures filling one respective longitudinal space between two respective wordlines. Furthermore, in a conventional process these longitudinal filling structures are patterned along the first direction, thereby etching a plurality of trenches at those positions where the contact structures (the local interconnects) are to be formed. Each trench extends through the complete thickness of the respective filling structure down to the substrate surface. Thereafter, conductive material is deposited and an upper position thereof is etched, thereby forming a plurality of contact structures in the trenches within the filling structures.
Thereby a semiconductor product is provided that comprises contact structures filled in vias, which vias are confined, on opposed sides along the first direction, by sidewalls of respective two portions of the filling structure (which portions have been separated from one another during trench etching). Along the second direction, the contact structures are confined by respective two wordlines (that is, by their spacers).
Each contact structure formed in this way contacts two active areas arranged at a distance from one another along the first direction. Typically, the width of the active area corresponds to the width of the trench isolation filling provided therebetween. The width of the contact structure in the first direction accordingly is approximately three times the width of an active area or of a trench isolation filling, along the first direction.
However, the exact value of the width of the contact structure along the first direction, that is in direction parallel to the main extension of the wordlines between which the contact structures are provided, varies with the vertical position within the contact structure. In particular, the width of the contact structure along the first direction, measured at the top side of the contact structure, usually is larger than the width of the contact structure along the first direction, measured at a bottom side of the contact structure. Conventionally, the width of the contact structure (that is its extension in the first direction) increases with increasing distance from the substrate surface. In a cross-sectional view the shape of the contact structure corresponds to a trapezium having its long base at the top side of the contact structure and having its short base on the substrate surface.
This shape of the contact structures result from the circumstance that the contact structures are etched into dielectric filling structures filling the spaces between the wordlines. Etching of the trenches to be filled with the contact structures is performed by dry etching, for instance by reactive ion etching. Due to the typical etching profile of this anisotropic etching technique, at the top side of the insulating filling structures the trenches are slightly wider than at the bottom of the insulating filling structures (that is on the substrate surface). The reason therefor is that the duration of contact between the etching component and the etched sidewall of the remaining portions of the insulating filling structure decreases with increasing depth of the trench.
Due to conventional lithographic patterning, microelectronic structures have lateral dimensions corresponding to the critical dimension. The magnitude of the critical dimension depends on the wavelength used for the specific technology of lithography. However, with a predefined critical dimension the lateral extensions of the microelectronic structures are defined.
In semiconductor manufacturing the risk of lateral misalignment occurs. Since a mask for etching the trenches in the dielectric filling structures may be misaligned along the first direction relative to the active areas, the trenches to be filled with the contact structures may be offset in the first direction with respect to the active areas to be contacted. Depending on the extent of such lateral offset, the contact interface surface between one of the two active areas to be contacted and the contact structure is less, in the first direction, than the critical dimension whereas the contact structure extends beyond the other active area in the first direction. Accordingly, any lateral offset in the first direction bears the risk of increased contact resistance between the contact structure (the local interconnect) and one of the two active areas to be contacted.
Furthermore, due to the sloped sidewalls of the contact structures seen in cross-sectional view parallel to the worldlines, the width of the contact structures, measured at the substrate surface along the first direction, is actually smaller than three times the critical dimension (at the top side the width of the contact structures exceed a magnitude of three times the critical dimension). Accordingly, even in the absence of any lateral offset in the first direction, the contact interface surface between the contact structure and each active area is smaller in the first direction than the critical dimension. Thereby the contact resistance between the active areas and the contact structures (the local interconnects) is further increased.